1. Field of the Invention
The present invention relates to a data processing system for transferring data in a burst mode transfer between a microprocessor and a memory which are coupled through a system bus.
2. Description of Related Art
Microprocessors show a yearly elevation of their performance and function, and the operating frequency is also elevating to 25 MHz, then to 33 MHz, and further to 50 MHz. On the other hand, an external memory ordinarily used for supplying instructions and data to the microprocessor has only a data transfer rate which is still lower than the operating speed of the microcomputer, although a memory having a high transfer rate has recently appeared but it is expensive. Therefore, the data transfer rate between the microprocessor and the memory has a large influence on overall performance of a system. Most recent microprocessors internally contain a cache memory so that frequently used data is stored in the cache memory for compensating for a difference in the data transfer rate between the microprocessor and the external memory. Even in this case, however, the data transfer rate in the data transfer from the external memory to the microprocessor lowers the performance of the system.
In most microprocessors internally containing the cache memory, the data transfer to the cache memory is performed in a burst mode. Here, the "burst mode" transfer means a data transfer manner in which data is continuously transferred from an external memory to a block having a series of continuous addresses.
One typical example of a synchronous burst transfer is disclosed in Japanese Patent Application Laid-open Publication JP-A-3-134754 titled "DATA PROCESSING SYSTEM", which will be now described with reference to FIG. 1. The data processing system includes a microprocessor 101, an address decoder 102, a memory control circuit 103a and a memory 104, which are coupled as shown. The microprocessor 101 and the memory 104 are coupled to an external data bus 109 so that data can be transferred through the external data bus 109 between the microprocessor 101 and the memory 104.
Operation of this data processing system in a burst mode transfer will be explained with reference to FIG. 2 showing a timing chart of the data transfer system. First, the microprocessor 101 outputs an effective address 105, and activates a bus cycle start signal (ADS) 106 and a read/write signal (R/W) 107. If an address region to be accessed comes within a cache region, the microprocessor 101 activates a synchronous block transfer request signal (BLOCK) 108.
The address decoder 102 decodes the received address 105, and informs the memory control circuit 103a of whether an address designated region is a high speed memory region or a middle or low speed memory region. In general, a microprocessor based system uses, as a memory, an EPROM (electrically programmable read only memory), DRAM (dynamic random access memory), SRAM (static random access memory), etc. which are selected on the basis of an address.
Since this selection of memory is made within a region of continuous addresses, the address decoder 102 can be formed by for example an address discrimination circuit shown in FIG. 3, which receives the most significant two bits A[31: 30] of a 32-bit address 105 and includes two inverters 140 and 142 and two AND circuits 141 and 143 connected as shown so as to discriminate the memory region (high speed, middle speed or low speed) on the basis of the most significant two bits A[31: 30] of the address.
When the address designated region is the high speed memory region, the memory control circuit 103a receiving the ADS signal 106, the R/W signal 107 and the BLOCK signal 108, outputs a chip select signal CS and a write/read signal WR to the memory 104, and activates a burst transfer enabling signal (BLOCKF) 201 so as to enable a burst transfer and to change the status in synchronism with operation of the microprocessor so as to control the memory. This status transition diagram is shown in FIG. 4. In accordance with the instruction of the BLOCKF signal 102, the microprocessor performs the burst transfer. Therefore, a synchronous burst mode transfer can be performed between the memory and the microprocessor.
When the address designated region is the middle or low speed memory region, the memory control circuit 103 does not enable the burst mode transfer by the burst mode transfer enabling signal BLOCKF 201 as shown in FIG. 5, but a non-burst mode transfer (asynchronous data transfer) in which data is transferred item by item, is performed. In this non-burst mode transfer, the memory control circuit 103 adjust a data set signal (DS) 202 supplied to the microprocessor 101, dependently upon a performance of a memory allocated to a designated address region, so that a time until a data access is adjusted. This DS signal 202 is generated from the ADS signal 106 by for example a circuit shown in FIG. 6, which receives the ADS signal 106 and includes two cascaded delay circuits 144 and 145 and a selector 146 receiving an output of each of the delay circuits and controlled on the basis of whether the designated address region is the middle speed memory region or the low speed memory region.
In the non-burst mode transfer, the above mentioned conventional system can comply with a memory having any performance. In addition, the conventional system can simplify the control of the status transition for the synchronous burst mode transfer, and therefore, can speed up the change of the cache address and the writing to the cache memory.
Now, as a second conventional example configured to perform the burst mode transfer in an asynchronous mode, the microprocessor "i486" available rom Intel Corporation in the U.S.A. will be explained with reference to FIG. 7. In FIG. 7, elements similar to those shown in FIG. 1 are given the same Reference Numerals.
As shown in FIG. 7, the microprocessor 101 outputs an effective address 105, and activates a bus cycle start signal (ADS) 106 and a read/write signal (R/W) 107. The address decoder 102 decodes the address 105 to discriminate an address designated region and to notify the result of the discrimination to a memory control circuit 103b.
The memory control circuit 103b receives the ADS signal 106 and the R/W signal 107. In addition, depending upon the performance of the memory 104 allocated to the address designated region, the memory control circuit 103b cyclicly changes a burst ready signal (BRDY) 203 indicating that data is set in the burst transfer mode, and also controls the memory 104. In accordance with the value of the BRDY signal 203, the microprocessor 101 changes its status as shown in the status transition diagram of FIG. 8, so that data is fetched into the microprocessor 101 from the memory 104.
Referring to FIG. 9, there is shown an example of a BRDY signal generating circuit 210 included in the memory control circuit 103b. This BRDY signal generating circuit 210 includes a down counter 211 for counting a delay value, an up counter 212 for counting the number of items to be transferred, a delay value setting circuit 213, delay circuits 144 and 145, inverters 147 and 148 and a selector 149, which are connected as shown.
First, an input value to be supplied to the down counter 211 is determined on the basis of the result of the address decoding. When the bus cycle starts, the up counter 212 is reset to "0" by the ADS signal 106. After one cycle from the ADS signal 106, a delay value is loaded to the down counter 211 from the delay value setting circuit 213, and after a further one cycle, the down counter starts its count-down operation so that the value of the down counter 211 is decremented for each clock. When the value of the down counter 211 becomes "0", the down counter 211 outputs a high level signal from its output "OUT", and then, returns to the delay value so as to restart its count-down operation. The output of the down counter 211 is inverted by the inverter 148 so as to generate the BRDY signal 203.
On the other hand, the up counter 212 counts up in response to the output of the down counter 211 so as to count the number of items transferred, as "0".fwdarw."1".fwdarw."2".fwdarw."3".fwdarw."4". When the value of the up counter 212 becomes "4", the up counter 212 generates a high level output signal, which is supplied to a stop input of the down counter 211, so that the down counter 211 stops its its count-down operation.
As mentioned above, since the status changes in accordance with the value of the BRDY signal 203, the data transfer between the microprocessor and the memory becomes an asynchronous burst transfer.
As examples of the operation timing of the second conventional system, FIG. 10 shows a timing chart of a no-wait burst mode transfer, and FIG. 11 shows a timing chart of a one-wait burst mode transfer. As seen from comparison between FIGS. 10 and 11, it is possible to control the wait in the burst mode transfer by the BRDY signal 203. In a middle speed DRAM memory, accordingly, the burst mode transfer becomes possible by using a page mode, and therefore, the data transfer rate can be increased in comparison with the non-burst mode transfer.
In the above mentioned first conventional example, in order to elevate the system performance by increasing the data transfer rate, it is necessary to increase a high speed memory which allows the burst mode transfer, which will result in an increased system cost. For example, assuming that the operating frequency of the microprocessor 101 is 33 MHz (one cycle=30 ns), the address output delay time is 10 ns, and the data input setting time is 10 ns, since the memory 104 is required to have the access time of not greater than 10 ns, an expensive SRAM becomes required. In order to suppress the system cost, if an inexpensive but low transfer rate memory is used and if the data transfer is performed in the non-burst mode transfer or if the clock frequency of the burst mode transfer is lowered, the performance inevitably greatly drops.
The first conventional example was effective when the processing speed of the microprocessor was not so high in comparison with the memory. However, as the processing speed of the microprocessor has remarkably elevated, the first conventional example can no longer meet with the recent technical trend, and therefore, the second conventional example has been adopted. However, the second conventional example has different problems.
In the second conventional example, after the BRDY signal 203 is fetched, a next internal status is fixed. Therefore, in the case of attempting to speed up the operation from the data fetching to the writing of the cache, the no-wait asynchronous burst mode transfer can write to the cache at the same timing as the conventional synchronous transfer shown in FIG. 4, as seen from FIG. 10. However, if the wait is inserted, as shown in FIG. 11, a cycle occupying the internal data bus is inserted to await for the data setting or fixing. Assuming that one block of the cache includes "m" words and the number of waits is "n", the number of cycles required for waiting for internal data setting or fixing becomes "m.times.n".
In order to minimize the number of cycles required for waiting for internal data setting or fixing (the internal bus occupation), if four stages of read buffer are provided to continuously write the cache memory, the timing becomes as shown in FIG. 12. As seen from comparison between FIG. 12 and FIG 10 in which the writing to the cache is speeded up, the time until the last data has been written is elongated by four cycles. In the asynchronous burst mode transfer, there is required an external counter for changing the period of the data setting signal.